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ICS16859C Scheda tecnica(PDF) 5 Page - Integrated Circuit Systems |
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ICS16859C Scheda tecnica(HTML) 5 Page - Integrated Circuit Systems |
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5 / 8 page ![]() 5 ICSSSTV16859C 0703A—10/15/02 Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1) MIN TYP MAX fmax 200 MHz CLK, CLK# (TSSOP) Q 1.7 2.3 2.7 ns CLK, CLK# (VFQFN[MLF2]) Q 1.6 2.1 2.6 ns tphl RESET# Q 3.5 ns SYMBOL VDD = 2.5V ±0.2V UNITS From (Input) To (Output) tPD Timing Requirements 1 (over recommended operating free-air temperature range, unless otherwise noted) MIN MAX fclock Clock frequency 200 MHz TSSOP 1.7 2.7 ns VFQFN [MLF2] 1.6 2.6 ns tRST Reset to output time 3.5 ns tSL Output slew rate 1 4 V/ns Setup time, fast slew rate 2 & 4 0.4 ns Setup time, slow slew rate 3 & 4 0.6 ns Hold time, fast slew rate 2 & 4 0.4 ns Hold time, slow slew rate 3 & 4 0.5 ns 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of ≥ 1V/ns. 4 - CLK, CLK# signals input slew rate of ≥ 1V/ns. 3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns. VDDQ = 2.5V ± 0.2V UNITS PARAMETERS Data before CLK ↑ , CLK#↓ Data after CLK ↑ , CLK#↓ Clock to output time SYMBOL tS Th Notes: tPD |
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