ICS848004I datasheet(7/11 Pages) ICST

7 / 11 page

848004AGI

www.icst.com/products/hiperclocks.html

REV. A AUGUST 18, 2005

Integrated

Circuit

Systems, Inc.

ICS848004I

FEMTOCLOCKS™CRYSTAL-TO-

SSTL_2 FREQUENCY SYNTHESIZER

PRELIMINARY

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS848004I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD, VDDA, and VDDO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 10

Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each V

DDA.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

DDA

μF

.01

μF

3.3V

.01

μF

CRYSTAL INPUT INTERFACE

The ICS848004I has been characterized with 18pF parallel reso-

nant crystals. The capacitor values shown in Figure 2 below

Figure 2. CRYSTAL INPUt INTERFACE

ICS848004I

33p

18pF Parallel Crystal

27p

XTAL_OUT

XTAL_IN

were determined using a 26.5625MHz 18pF parallel resonant

crystal and were chosen to minimize the ppm error.

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