P5021 datasheet(91/155 Pages) NXP

Il numero della parte	P5021

Spiegazioni elettronici	P5021 QorIQ Integrated Processor Data Sheet

PDF	155 Pages

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Produttore elettronici	NXP [NXP Semiconductors]

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

This figure shows the AC timing diagram of the local bus interface.

Figure 24. Enhanced local bus signals

Figure 25 applies to all three controllers that eLBC supports: GPCM, UPM, and FCM.

For input signals, the local bus AC timing data is used directly for all three controllers.

For output signals, each type of controller provides its own unique method to control the signal timing. The final signal delay

value for output signals is the programmed delay plus the AC timing delay. For example, for GPCM, LCS can be programmed

to delay by tacs (0, ¼, ½, 1, 1 + ¼, 1 + ½, 2, 3 cycles), so the final delay is tacs + tLBKLOV.

Output Signals

tLBKLOX

LCLK[m]

Input Signals

LALE

tLBIXKH

tLBIVKH

tLBIVKL

tLBIXKL

Input Signal

tLBONOT

(LGTA/LUPWAIT/LFRB)

(Except LGTA/LUPWAIT/LFRB)

(Except LALE)

LAD

(address phase)

LAD/LDP

(data phase)

tLBKLOZ

tLBKLOV

P5021 Scheda tecnica(PDF) 91 Page - NXP Semiconductors