SST26VF040A-80ISLASHMFVAO datasheet(61/73 Pages) MICROCHIP

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DS20006292B-page 61

SST26VF040A

32H

A16

F1H

Supports (1-1-2) Fast Read

0: (1-1-2) Fast Read NOT supported

1: (1-1-2) Fast Read supported

A18:A17

Address Bytes

Number of bytes used in addressing Flash array read, write and erase

00: 3-Byte only addressing

01: 3- or 4-Byte addressing (e.g., defaults to 3-Byte mode; enters 4-Byte

mode on command)

10: 4-Byte only addressing

11: Reserved

A19

Supports Double Transfer Rate (DTR) Clocking

Indicates the device supports some type of double transfer rate clocking.

0: DTR NOT supported

1: DTR Clocking supported

A20

Supports (1-2-2) Fast Read

Device supports single input opcode, dual input address, and dual output

data Fast Read.

0: (1-2-2) Fast Read NOT supported

1: (1-2-2) Fast Read supported

A21

Supports (1-4-4) Fast Read

Device supports single input opcode, quad input address, and quad output

data Fast Read

0: (1-4-4) Fast Read NOT supported

1: (1-4-4) Fast Read supported

A22

Supports (1-1-4) Fast Read

Device supports single input opcode & address and quad output data Fast

Read.

0: (1-1-4) Fast Read NOT supported

1: (1-1-4) Fast Read supported

A23

Unused. Contains ‘1’ cannot be changed.

33H

A31:A24

FFH

Unused. Contains FF cannot be changed.

JEDEC Flash Parameter Table: 2nd DWORD

34H

A7:A0

FFH

Flash Memory Density

SST26VF040A = 003FFFFFH

35H

A15:A8

FFH

36H

A23:A16

3FH

37H

A31:A24

00H

JEDEC Flash Parameter Table: 3rd DWORD

38H

A4:A0

44H

(1-4-4) Fast Read Number of Wait states (dummy clocks) needed before

valid output

00100b: 4 dummy clocks (16 dummy bits) are needed with a Quad Input

Address Phase instruction.

A7:A5

Quad Input Address Quad Output (1-4-4) Fast Read Number of Mode

Bits

010b: 2 dummy clocks (8 mode bits) are needed with a single input opcode,

quad input address and quad output data Fast Read instruction.

39H

A15:A8

EBH

(1-4-4) Fast Read Opcode

Opcode for single input opcode, quad input address and quad output data

Fast Read instruction.

TABLE 11-1:

SERIAL FLASH DISCOVERABLE PARAMETER (SFDP) (SHEET 3 OF 13)

Address

Bit

Address

Data

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