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Z84C9012VSC Scheda tecnica(PDF) 14 Page - Zilog, Inc. |
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Z84C9012VSC Scheda tecnica(HTML) 14 Page - Zilog, Inc. |
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14 / 31 page  Z84C90 KIO Serial/Parallel Counter Timer PS011802-0902 9 Standard Test Conditions The DC Characteristics and Capacitance sections below apply to the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (0V). Posi- tive current flows into the referenced pin. Available operating temperature ranges are: • S = 0° C to +70° C • E = –40° C to +100° C Voltage Supply Range: +5.0V ± 10% All AC parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for the address and control lines. AC timing measurements are referenced to 1.5 volts (except for CLOCK, which is referenced to the 10% and 90% points. Table 2. KIO Registers Address A3 A2 A1 A0 Register 0: PIO Port A Data 0 0 0 0 Register 1: PIO Port A Command 0 0 0 1 Register 2: PIO Port B Data 0 0 1 0 Register 3: PIO Port B Command 0 0 1 1 Register 4: CTC Channel 0 0 1 0 0 Register 5: CTC Channel 1 0 1 0 1 Register 6: 0 1 1 0 Register 7: 0 1 1 1 Register 8: SIO Port A Data 1 0 0 0 Register 9: SIO Port A Command/Status 1 0 0 1 Register 10: SIO Channel B Data 1 0 1 0 Register 11: SIO Channel B Command/Status 1 0 1 1 Register 12: PIA Port C Data 1 1 0 0 Register 13: PIA Port C Command 1 1 0 1 Register 14: KIO Command 1 1 1 0 Register 15: Reserved 1 1 1 1 Note: Additionally, IORQ and CS must be Low. Registers are written to or read from by the CPU, applying a 1 or a 0 respectively on the RD pin. |
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