P87LPC779 datasheet(49/74 Pages) PHILIPS

49 / 74 page

Philips Semiconductors

P87LPC779

CMOS single-chip 8-bit microcontroller

Product data

Rev. 02 — 03 May 2004

49 of 74

9397 750 13213

[1]

Tables 39 and 40 apply to UART modes 1 and 3 (variable rate modes), and show CPU clock rates in MHz for standard baud rates from

2400 to 115.2 kbaud.

[2]

Table 39 shows timer settings and CPU clock rates with the SMOD1 bit in the PCON register = 0 (the default after reset), while Table 40

reﬂects the SMOD1 bit = 1.

[3]

The tables show all potential CPU clock frequencies up to 20 MHz that may be used for baud rates from 9600 baud to 115.2 kbaud.

Other CPU clock frequencies that would give only lower baud rates are not shown.

[4]

Table entries marked with an asterisk (*) indicate standard crystal and ceramic resonator frequencies that may be obtained from many

sources without special ordering.

8.15.8

More about UART Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted/received: 8 data bits (LSB ﬁrst). The baud rate is ﬁxed at 1

⁄

6 the CPU

clock frequency. Figure 23 shows a simpliﬁed functional diagram of the serial port in

Mode 0, and associated timing.

Transmission is initiated by any instruction that uses SBUF as a destination register.

The ‘write to SBUF’ signal at S6P2 also loads a ‘1’ into the 9th position of the transmit

shift register and tells the TX Control block to commence a transmission. The internal

timing is such that one full machine cycle will elapse between ‘write to SBUF’ and

activation of SEND.

SEND enables the output of the shift register to the alternate output function line of

P3.0 and also enable SHIFT CLOCK to the alternate output function line of P3.1.

SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during

S6, S1, and S2. At S6P2 of every machine cycle in which SEND is active, the

contents of the transmit shift are shifted to the right one position.

As data bits shift out to the right, zeros come in from the left. When the MSB of the

data byte is at the output position of the shift register, then the ‘1’ that was initially

loaded into the 9th position, is just to the left of the MSB, and all positions to the left of

that contain zeros. This condition ﬂags the TX Control block to do one last shift and

then deactivate SEND and set T1. Both of these actions occur at S1P1 of the 10th

machine cycle after ‘write to SBUF.’ Reception is initiated by the condition REN = 1

and R1 = 0. At S6P2 of the next machine cycle, the RX Control unit writes the bits

11111110 t o the receive shift register, and in the next clock phase activates

RECEIVE.

−15

3.4560

6.9120

13.8240

−16

* 3.6864

* 7.3728

* 14.7456

−17

3.9168

7.8336

15.6672

−18

4.1472

8.2944

16.5888

−19

4.3776

8.7552

17.5104

−20

4.6080

9.2160

* 18.4320

−21

4.8384

9.6768

19.3536

Table 40:

Baud rates, timer values, and CPU clock frequencies for SMOD1 = 1…continued

Timer Value

Baud Rate

2400

4800

9600

19.2 k

38.4 k

57.6 k

115.2 k

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