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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SH7041A Scheda tecnica(PDF) 345 Page - Renesas Technology Corp |
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SH7041A Scheda tecnica(HTML) 345 Page - Renesas Technology Corp |
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345 / 923 page  307 Channels 1, 2: TIER1, TIER2: Bit: 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value: 0 1 0 0 0 0 0 0 R/W: R/W R R/W R/W R R R/W R/W Channels 3, 4: TIER3, TIER4: Bit: 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value: 0 1 0 0 0 0 0 0 R/W: R/W R R R/W R/W R/W R/W R/W • Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of an A/D conversion start request by a TGRA register input capture/compare-match. Bit 7: TTGE Description 0 Disable A/D conversion start requests (initial value) 1 Enable A/D conversion start request generation • Bit 6—Reserved: This bit is reserved. It always reads as 0, and cannot be modified. • Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests when the underflow flag (TCFU) of the channel 1, 2 timer status register (TSR) is set to 1. This bit is reserved for channels 0, 3, and 4. It always reads as 0. The write value should always be 1. Bit 5: TCIEU Description 0 Disable UDF interrupt requests (TCIU) (initial value) 1 Enable UDF interrupt requests (TCIU) • Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests when the overflow flag TCFV of the timer status register (TSR) is set to 1. Bit 4: TCIEVDescription 0 Disable TCFV interrupt requests (TCIV) (initial value) 1 Enable TCFV interrupt requests (TCIV) |
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