SH7041A datasheet(28/923 Pages) RENESAS

28 / 923 page

11.1.2 Block Diagram...................................................................................................... 215

11.1.3 Pin Configuration ................................................................................................. 216

11.1.4 Register Configuration ......................................................................................... 217

11.2

Register Descriptions......................................................................................................... 218

11.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)........................................... 218

11.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3) .................................. 219

11.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 220

11.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3) ................................... 221

11.2.5 DMAC Operation Register (DMAOR) ................................................................ 226

11.3

Operation ........................................................................................................................... 228

11.3.1 DMA Transfer Flow ............................................................................................. 228

11.3.2 DMA Transfer Requests....................................................................................... 230

11.3.3 Channel Priority.................................................................................................... 232

11.3.4 DMA Transfer Types ........................................................................................... 235

11.3.5 Address Modes ..................................................................................................... 235

11.3.6 Dual Address Mode .............................................................................................. 237

11.3.7 Bus Modes ............................................................................................................ 244

11.3.8 Relationship between Request Modes and Bus Modes by DMA Transfer

Category ............................................................................................................... 245

11.3.9 Bus Mode and Channel Priority Order ................................................................. 246

11.3.10 Number of Bus Cycle States and

DREQ Pin Sample Timing .............................. 246

11.3.11 Source Address Reload Function ......................................................................... 263

11.3.12 DMA Transfer Ending Conditions ....................................................................... 264

11.3.13 DMAC Access from CPU .................................................................................... 265

11.4

Examples of Use ................................................................................................................ 265

11.4.1 Example of DMA Transfer between On-Chip SCI and External Memory .......... 265

11.4.2 Example of DMA Transfer between External RAM and External Device

with DACK........................................................................................................... 266

11.4.3 Example of DMA Transfer between A/D Converter and On-Chip Memory

(Address Reload On) (Excluding A Mask) .......................................................... 266

11.4.4 Example of DMA Transfer between A/D Converter and Internal Memory

(Address Reload On) (A Mask) ............................................................................ 268

11.4.5 Example of DMA Transfer between External Memory and SCI1 Send Side

(Indirect Address On) ........................................................................................... 270

11.5

Cautions on Use................................................................................................................. 272

Section 12 Multifunction Timer Pulse Unit (MTU) .................................................. 273

12.1

Overview............................................................................................................................ 273

12.1.1 Features................................................................................................................. 273

12.1.2 Block Diagram...................................................................................................... 276

12.1.3 Pin Configuration ................................................................................................. 278

12.1.4 Register Configuration ......................................................................................... 280

12.2

MTU Register Descriptions............................................................................................... 283

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