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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SH7041A Scheda tecnica(PDF) 504 Page - Renesas Technology Corp |
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SH7041A Scheda tecnica(HTML) 504 Page - Renesas Technology Corp |
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504 / 923 page  466 13.4Notes on Use 13.4.1 TCNT Write and Increment Contention If a timer counter (TCNT) increment clock pulse is generated during the T3 state of a write cycle to the TCNT, the write takes priority and the timer counter is not incremented (figure 13.8). CK Address Internal write signal TCNT input clock TCNT NM TCNT address Counter write data T1 T2 T3 TCNT write cycle Figure 13.8 Contention between TCNT Write and Increment 13.4.2 Changing CKS2–CKS0 Bit Values If the values of bits CKS2–CKS0 are altered while the WDT is running, the count may increment incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the values of bits CKS2–CKS0. 13.4.3 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. |
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