7 Detailed Description

7.1 Overview

The configuration bit stream stored in the DLPR410 device supports reliable operation of the DLPC410ZYR

device with the DLP650LNIRFYL, DLP7000FLP, DLP7000UVFLP, DLP9500FLN and, DLP9500UVFLN DMDs.

DMDs. The DLPC410ZYR digital controller loads this configuration bit stream from the DLPR410 device.

7.2 Functional Block Diagram

DLPR410

TCK

TDI

TMS

OE/RESET

CLKOUT

CE

CF

EN_EXT_SEL

REV_SEL0

REV_SEL1

D0

TDO

CEO

Figure 7-1. Functional Block Diagram

7.3 Feature Description

7.3.1 Data Interface

7.3.1.1 Data Outputs

The DLPR410 device is configured for serial mode operation, where D0 is the data output pin. D0 output

pin provides a serial connection to the DLPC410ZYR controller, where the configuration is read out by the

DLPC410ZYR controller.

7.3.1.2 Configuration Clock Input

The configuration CLK is connected to the DLPC410ZYR controller in Primary Serial mode, where the

DLPC410ZYR controller provides the clock pulses to read the configuration from the DLPR410 device.

7.3.1.3 Output Enable and Reset

When the OE/ RESET input is held low, the address counter is reset and the Data (D0) and CLKOUT outputs

are placed in high-impedance state. OE/ RESET must be pulled High using an external 4.7-kΩ pull-up to

7.3.1.4 Chip Enable

The CE input is asserted by the DLPC410ZYR controller to enable the Data (D0) and CLKOUT outputs. When

CE is held high, the DLPR410 device address counter is reset, and the Data and CLKOUT outputs are placed in

high-impedance states.

DLPR410

DLPS027G – AUGUST 2012 – REVISED AUGUST 2021

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