ADP2311ACPZ-2-R7 datasheet(14/20 Pages) AD

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ADP2311

Data Sheet

Rev. B | Page 14 of 20

The POR function has hysteresis of 1.5% between the falling and

rising thresholds. The POR rising threshold is 96.5% typical,

95% minimum, and 98% maximum. Therefore, the typical POR

rising trigger voltage is 0.6 V × 96.5% = 0.579 V. The POR rising

threshold voltage is always higher than the POR falling threshold

voltage.

TIMER PIN CONFIGURATION

The POR sequence timing and delay time depend on the config-

uration of the TIMER pin.

Figure 31 shows the first configuration of the TIMER pin.

Figure 34 shows the power-on reset timing for this configuration.

As shown in Figure 31, a capacitor is connected between the

TIMER pin and GND. The POR pin is pulled high when both

VOUT1 and VOUT2 are above 96.5% of the VOUTx nominal value

after a delay time. The POR pin is pulled low when either VOUT1

or VOUT2 falls below 95% of the VOUTx nominal voltage.

The POR delay time is determined by the maximum value

between the internal default delay of 1.7 ms and an external

delay time calculated by the following equation:

TIMER

DELAY





0.6

where:

CTIMER

is the capacitor between the TIMER pin and GND

(1 nF to 68 nF).

ITIMER

is the pull-up current of the TIMER pin (3 μA).

Figure 32 shows the second configuration of the TIMER pin.

Figure 35 shows the power-on reset timing for this configuration.

As shown in Figure 32, a resistor and capacitor are connected

between the TIMER pin and GND. The POR pin is pulled high

when both VOUT1 and VOUT2 are above 96.5% of the VOUTx nominal

value after a delay time. The POR pin is pulled low when VOUT1

or VOUT2 falls below 95% of the VOUTx nominal voltage or when

the watchdog timer times out (the RSTO pin is taken from high

to low).

The POR delay time is determined by the maximum value

between the internal default delay of 1.7 ms and an external

delay time calculated by the following equation:



TIMER

SEQ

TIMER

DELAY







where:

RSEQ is a resistor in the range of 8 kΩ to 12 kΩ. Typically,

a 10 kΩ resistor is chosen for RSEQ.

CTIMER is a capacitor in the range of 1 nF to 68 nF.

Figure 33 shows the third configuration of the TIMER pin.

Figure 35 shows the power-on reset timing for this configuration.

In this configuration, the TIMER pin is floating. The POR delay

time is fixed at 1.7 ms.

ADP2311

TIMER

CTIMER

POR

RSTO

Figure 31. Capacitor Connected Between TIMER and GND

CTIMER

ADP2311

TIMER

RSEQ

POR

RSEQ = 10kΩ

RSTO

Figure 32. Resistor and Capacitor Connected Between TIMER and GND

ADP2311

TIMER

POR

RSTO

Figure 33. TIMER Pin Floating

VOUT1

tWD

WDI

VOUT2

POR

tDELAY

96.5% × VOUT1

96.5% × VOUT2

95% × VOUT2

tRP

RSTO

Figure 34. Power-On Reset Timing for Figure 31

WDI

VOUT2

POR

tWD

tRP

VOUT1

tDELAY

96.5% × VOUT1

96.5% × VOUT2

95% × VOUT2

RSTO

Figure 35. Power-On Reset Timing for Figure 32 and Figure 33

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