USB7016TSLASHKDX datasheet(7/59 Pages) MICROCHIP

7 / 59 page

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2021 Microchip Technology Inc.

DS00003740A-page 7

USB7016

Port Split, which allows for the USB 3.2 Gen 1 and USB 2.0 portions of downstream ports 2, 3, and 4 in Configuration

1 and downstream port 4 (only) in Configuration 2 to operate independently and enumerate two separate devices in

parallel in special applications.

USB Power Delivery Billboard Device, which allows an internal device to enumerate as a Billboard class device when

a Power Delivery Alternate Mode negotiation has failed. The Billboard device will enumerate temporarily to the host PC

when a failure occurs, as indicated by a digital signal from an external Power Delivery controller.

The USB7016 can be configured for operation through internal default settings. Custom OEM configurations are sup-

ported through external SPI ROM or OTP ROM. All port control signal pins are under firmware control in order to allow

for maximum operational flexibility and are available as GPIOs for customer specific use.

The USB7016 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range. An internal

block diagram of the USB7016 in an upstream Type-B application is shown in Figure 2-1.

FIGURE 2-1:

USB7016 INTERNAL BLOCK DIAGRAM - UPSTREAM TYPE-B APPLICATION

Note:

All port numbering in this document is LOGICAL port numbering with the device in the default configuration.

LOGICAL port numbering is the numbering as communicated to the USB host. It is the end result after any

port number remapping or port disabling. The PHYSICAL port number is the port number with respect to

the physical PHY on the chip. PHYSICAL port numbering is fixed and the settings are not impacted by

LOGICAL port renumbering/remapping. Certain port settings are made with respect to LOGICAL port num-

bering, and other port settings are made with respect to PHYSICAL port numbering. Refer to the “Config-

uration of USB70xx Family” application note for details on the LOGICAL vs. PHYSICAL mapping and

additional configuration details.

Hub Controller Logic

I2C/SPI

25 Mhz

USB3 USB2

‘A’

USB7016

+3.3 V

VCORE

PHY2

PHY1

PHY2

‘B’

PHY1

‘A’

‘C’

‘A’

PHY3 PHY3

‘A’

PHY4 PHY4

‘A’

PHY5 PHY5

‘A’

PHY6

Hub Feature Controller

GPIO SMB

OTP

SPI

Mux

HFC

PHY

PHY0

‘B’

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