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Data Sheet

ADP5304

Rev. 0 | Page 11 of 17

THEORY OF OPERATION

The ADP5304 is a high efficient, ultralow quiescent current

step-down regulator in a 10-lead LFCSP package, designed to

meet demanding performance and board space requirements.

The device enables direct connection to a wide input voltage

range of 2.15 V to 6.50 V, allowing the use of high impedance

power sources or energy harvester sources.

BUCK REGULATOR OPERATIONAL MODE

The ADP5304 buck regulator operates in hysteresis mode and

charges the output voltage slightly higher than its nominal

output voltage with PWM pulses via the regulation of constant

peak inductor current. When the output voltage increases until

the output sense signal exceeds the hysteresis upper threshold,

the regulator enters the standby mode. In standby mode, the

high-side and low-side MOSFET and a majority of the circuitry

are disabled to allow a low quiescent current, as well as high

efficiency performance. During standby mode, the output

capacitor supplies the energy into the load and the output

voltage decreases until it falls below the hysteresis comparator

lower threshold. Then, the buck regulator wakes up into active

mode and generates the PWM pulses to charge the output again.

The buck regulator is forced to operate in hysteresis mode via

connecting the MODE pin to ground. The regulator only draws

260 nA of quiescent current to regulate the output under zero load,

which allows the regulator to act as keep-alive power supply in

battery-powered applications or energy harvesting systems.

ADJUSTABLE AND FIXED OUTPUT VOLTAGES

The ADP5304 provides adjustable output voltage settings via

the connection of one resistor through the VID pin to AGND.

The VID detection circuitry works in the start-up period, and

the voltage ID code is sampled and held into the internal

Furthermore, the ADP5304 provides a fixed output voltage

programmed via the factory fuse. In this condition, connect

the VID pin to the PVIN pin.

For output voltage settings, the feedback resistor divider is built

in to the ADP5304, and the feedback pin (FB) must be tied

directly to the output. An ultralow power voltage reference and

an integrated high impedance (50 MΩ, typical) feedback

divider network contribute to low quiescent current. Table 5

lists the output voltage options by the VID pin configurations. It

is recommended to use a 1% resistor.

Table 5. Output Voltage Options by the VID Pin

VID

Configuration

VOUT,

Factory Option 0 (V)

VOUT,

Factory Option 1 (V)

Short to ground

3.0

3.1

Short to PVIN

2.5

1.3

RVID = 499 kΩ

3.6

5.0

RVID = 316 kΩ

3.3

4.5

RVID = 226 kΩ

2.9

4.2

RVID = 174 kΩ

2.8

3.9

RVID = 127 kΩ

2.7

3.4

RVID = 97.6 kΩ

2.6

3.2

RVID = 76.8 kΩ

2.4

1.9

RVID = 56.2 kΩ

2.3

1.7

RVID = 43 kΩ

2.2

1.6

RVID = 32.4 kΩ

2.1

1.4

RVID = 25.5 kΩ

2.0

1.1

RVID = 19.6 kΩ

1.8

1.0

RVID = 15 kΩ

1.5

0.9

RVID = 11.8 kΩ

1.2

0.8

UNDERVOLTAGE LOCKOUT (UVLO)

The undervoltage lockout circuitry monitors the input voltage

level on the PVIN pin. If input voltage falls below 2.00 V

(typical), the regulator turns off. After the input voltage rises

above 2.06 V (typical), the soft start period initiates, and when

the EN pin is high, the regulator enables.

ENABLE/DISABLE

The ADP5304 includes a separate enable (EN) pin. A logic high

on the EN pin starts the regulator. Due to the low quiescent current

design, it is typical for the regulator to start switching after a

delay of a few milliseconds from the EN pin being pulled high.

A logic low on the EN pin immediately disables the regulator

and brings the regulator into extremely low current consumption.

VINOK FUNCTION

The ADP5304 includes an open-drain VINOK output that can

be used to indicate the input voltage status. The VINOK output

becomes active high when the input voltage on the PVIN pin is

above the reference threshold. When the input voltage falls below

the reference threshold, the VINOK pin goes low. Note that a

relatively long validation time of 130 μs typical exists for the

VINOK output status to change due to the ultralow power

comparator design.

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