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AM79C850 Scheda tecnica(PDF) 45 Page - Advanced Micro Devices |
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AM79C850 Scheda tecnica(HTML) 45 Page - Advanced Micro Devices |
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45 / 97 page ![]() P R E L I M I N A R Y AMD 45 SUPERNET 3 Status Register 3 (ST3U & ST3L) A 32-bit read only register, designated ST3, and a 32 bit read/write register, designated IMSK3, has been added in SUPERNET 3. This register is dedicated to status handling and interrupt reporting. Any of the bits in this status register can be used generate an interrupt. The bits in ST3 may be masked by the interrupt mask registers (IMSK3) for complete control of the interrupt conditions. ST3 has status bits associated with receive operation for RECV2 queue, status of internal CAM match operation, and BIST operation for the various sub-blocks of the SUPERNET 3. All status bits except SRBMT2 and SRBFL2 are auto-cleared on reading the register. The remaining bits are set/reset depending upon the state of the monitored conditions. Refer to Interrupt Mechanisms for more detailed information regarding interrupt handling. LSB MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 19574A-16 SRQUNLCK1 SRPERRQ1 SRPERRQ2 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SRCVOVR2 SRBFL2 SRABT2 SRBMT2 SRCOMP2 SRQUNLCK2 Figure 15. Status Register 3 – Upper 16 Bits (ST3U) (NPADDR = 61h) |
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