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AM79C850KC Scheda tecnica(PDF) 72 Page - Advanced Micro Devices |
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AM79C850KC Scheda tecnica(HTML) 72 Page - Advanced Micro Devices |
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72 / 97 page ![]() AMD P R E L I M I N A R Y 72 SUPERNET 3 SUPERNET 3 Programmable Registers (continued) Register Mnemonic NPADDR7–0 Description “imsk3l” “64” Lower 16 bits of IMSK register 3 “ivr” “65” Interrupt Vector register (Read Only) “imr” “66” Interrupt mask register “ilr” “67” (Hidden) “rpr2” “68” Read pointer for second receive queue “wpr2” “69” Write pointer for second receive queue “swpr2” “6a” Shadow write pointer for second receive queue “earv2” “6b” End Address of Receive 2 Queue “unlckdly” “6c” Auto Unlock Delay Register “6d” “6d” “6e” “6e” “lwpr1” “6f” (Hidden) “lrwd1” “70” (Hidden) “lwpr2” “71” (Hidden) “lrwd2” “72” (Hidden) “fifoflag” “73” (Hidden) “74” “74” “75” “75” “76” “76” “77” “77” “78” “78” “ltdpa1” “79” Last Transmit Descriptor Pointer for Async 1 queue “lsa0” “7a” (Hidden) “lss” “7b” (Hidden) “7c” “7c” “7d” “7d” “7e” “7e” “7f” “7f” “plc_cntrl_a” “80” PLC–S control register A “plc_cntrl_b” “81” PLC–S control register B “intr_mask” “82” PLC–S interrupt mask register “xmit_vector” “83” PLC–S transmit vector register “vector_length” “84” PLC–S vector length register “le_threshold” “85” PLC–S link error threshold register |
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