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ADIN1300BCPZ-R7 Scheda tecnica(PDF) 7 Page - Analog Devices

Il numero della parte ADIN1300BCPZ-R7
Spiegazioni elettronici  Robust, Industrial, Low Latency and Low Power 10 Mbps
PDF  79 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADIN1300BCPZ-R7 Scheda tecnica(HTML) 7 Page - Analog Devices

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Data Sheet
ADIN1300
Rev. 0 | Page 7 of 79
CONFIGURATION
LATCHED
DUAL FUNCTION
PINS ENABLED AS OUTPUTS
t3
t1
RESET RELEASED
CLOCK STABILISING
HARDWARE
CONFIG LATCHED
HARDWARE
POWERDOWN
MANAGEMENT
INTERFACE ACTIVE
MANAGEMENT
INTERFACE ACTIVE
t4
t2
XTAL_I
RESET_N
PIN
MDC
HARDWARE
BOOTSTRAP
PINS
FUNCTIONAL
STATE
Figure 3. Hardware Reset Timing
Management Interface Timing
Table 4. Management Interface Timing
Parameter
Description
Min
Typ
Max
Unit
t1
MDC period
180
ns
t2
MDC high time
70
ns
t3
MDC low time
70
ns
t4
MDC rise/fall time
5
ns
t5
MDIO signal setup time to MDC
10
ns
t6
MDIO signal hold time to MDC
10
ns
t7
MDIO delay time to MDC
0
60
ns
MDC
MDIO
INPUT
MDC
MDIO
OUTPUT
t2
t3
t1
t5
t6
t4
t4
t7
Figure 4. Management Interface Timing
MII Transmit and Receive Timing
Table 5. MII 100BASE-TX Transmit Timing
Parameter
Description
Min
Typ
Max
Unit
t1
TX_CLK period
40
ns
t2
TX_CLK high time
14
20
26
ns
t3
TX_CLK low time
14
20
26
ns
t4
TX_CLK rise/fall time
5
ns
t5
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) setup time to TX_CLK
10
ns
t6
MII input signal (TXD_0 to TXD_3, TX_EN, TX_ER) hold time to TX_CLK
0
ns



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