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PFD1K Scheda tecnica(PDF) 5 Page - Microsemi Corporation |
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PFD1K Scheda tecnica(HTML) 5 Page - Microsemi Corporation |
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5 / 19 page ![]() 5 of 19 SMD-00191 Rev D Subject to Change Without Notice PFD1K Control Logic Circuitry: The same circuitry is used for all control lines: A[0:3], R[0:6], V[0:6] and POL. A control pin left open defaults to logic 0. Analog Amplitude Controls: As was previously mentioned, VADJ can be used for fine tuning the charge pump current. Maximum current is achieved by setting VADJ to VCC. Similarly, the amplitudes of the prescaler outputs at DRO and DVO can be controlled with analog voltages VADR and VADV, respectively. As with VADJ, setting VADR and VADV to VCC results in maximum output amplitude. Simplified Control Logic Input Logic Level Minimum Typical Maximum 1 (High) VCC-1.3 V VCC VCC 0 (Low) VEE VEE VEE+0.8 V Table 1: Control Voltages (LVTTL Compatible) |
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