9 Power Supply Recommendations

The OPAx387 family of devices is specified for operation from 1.7 V to 5.5 V for single supplies, and ±0.85 V to

±2.75 V for dual supplies. Key parameters that can exhibit significant variance with regard to operating voltage

are presented in Section 6.7.

CAUTION

Supply voltages greater than 6 V can permanently damage the device (see Section 6.1).

10 Layout

10.1 Layout Guidelines

Pay attention to good layout practice. Keep traces short and, when possible, use a printed-circuit board (PCB)

ground plane with surface-mount components placed as close to the device pins as possible. Place a 0.1-µF

capacitor close to the supply pins. These guidelines must be applied throughout the analog circuit to improve

performance, and provide benefits such as reducing the electromagnetic interference (EMI) susceptibility.

For lowest offset voltage and precision performance, optimize circuit layout and mechanical conditions. Avoid

temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed from

connecting dissimilar conductors. Cancel these thermally-generated potentials by making sure that the potentials

are equal on both input terminals. Other layout and design considerations include:

• Use low thermoelectric-coefficient conditions (avoid dissimilar metals).

• Thermally isolate components from power supplies or other heat sources.

• Shield operational amplifier and input circuitry from air currents, such as cooling fans.

Follow these guidelines to reduce the likelihood of junctions being at different temperatures, which can cause

thermoelectric voltage drift of 0.1 µV/°C or higher depending on materials used.

10.2 Layout Example

+

V

IN

V

OUT

R

G

R

F

R

IN

Figure 10-1. Schematic Representation

OUT A

±IN A

+IN A

V±

V+

VS+

VS±

GND

Ground (GND) plane on another layer

VOUT

VIN

GND

Run the input traces

as far away from

the supply lines

as possible

Place components close

to device and to each

other to reduce parasitic

errors

Use low-ESR,

ceramic bypass

capacitor

GND

Use a low-ESR,

ceramic bypass

capacitor

±IN B

+IN B

OUT B

GND

VIN

VOUT

Place components

close to device

and to each other

to reduce parasitic

errors

Run the input traces

as far away from

the supply lines

as possible

Figure 10-2. Layout Example

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OPA387, OPA2387, OPA4387

SBOS984E – NOVEMBER 2020 – REVISED DECEMBER 2021

Copyright © 2021 Texas Instruments Incorporated

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