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AD9540PCB Scheda tecnica(PDF) 6 Page - Analog Devices

Il numero della parte AD9540PCB
Spiegazioni elettronici  655 MHz Low Jitter Clock Generator
PDF  32 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

AD9540PCB Scheda tecnica(HTML) 6 Page - Analog Devices

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AD9540
Rev. 0 | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CML OUTPUT DRIVER (OUT0)
Differential Output Voltage Swing5
720
mV
50 Ω load to supply, both lines
Maximum Toggle Rate
655
Common-Mode Output Voltage
1.75
V
Output Duty Cycle
42
58
%
Output Current
Continuous6
7.2
mA
Rising Edge Surge
20.9
mA
Falling Edge Surge
13.5
mA
Output Rise Time
250
ps
100 Ω terminated, 5 pF load
Output Fall Time
250
ps
100 Ω terminated, 5 pF load
LOGIC INPUTS (SDI/O, I/O_RESET, RESET,
I/O_UPDATE, S0, S1, S2, SYNC_IN)7
VIH, Input High Voltage
2.0
V
VIL, Input Low Voltage
0.8
V
IINH, IINL, Input Current
±1
±5
µA
CIN, Maximum Input Capacitance
3
pF
LOGIC OUTPUTS (SDO, SYNC_OUT, STATUS)8
VOH, Output High Voltage
2.7
V
VOH, Output Low Voltage
0.4
V
IOH
100
µA
IOL
100
µA
POWER CONSUMPTION
Total Power Consumed, All Functions On
400
mW
IAVDD
85
mA
IDVDD
45
mA
IDVDD_I/O
20
mA
ICPVDD
15
mA
Power-Down Mode
80
mW
WAKE-UP TIME (FROM POWER-DOWN MODE)
Digital Power-Down (CFR1<7>)
12
ns
DAC Power-Down (CFR2<39>)
7
µs
RF Divider Power-Down (CFR2<23>)
400
ns
Clock Driver Power-Down (CFR2<20>)
6
µs
Charge Pump Full Power-Down (CFR2<4>)
10
µs
Charge Pump Quick Power-Down (CFR2<3>)
150
ns
CRYSTAL OSCILLATOR (ON REFIN INPUT)
Operating Range
20
25
30
MHz
Residual Phase Noise (@ 25 MHz)
@ 10 Hz Offset
95
dBc/Hz
@ 100 Hz Offset
120
dBc/Hz
@ 1 kHz Offset
140
dBc/Hz
@ 10 kHz Offset
157
dBc/Hz
@ 100 kHz Offset
164
dBc/Hz
>1 MHz Offset
168
dBc/Hz
DIGITAL TIMING SPECIFICATIONS
CS to SCLK Setup Time TPRE
6
ns
Period of SCLK (Write) TSCLKW
40
ns
Period of SCLK (Read) TSCLKR
400
ns
Serial Data Setup Time TDSU
6.5
ns
Serial Data Hold Time TDHD
0
ns
Data Valid Time TDV
40
ns



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