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48SWTQFN-EP Scheda tecnica(PDF) 12 Page - Maxim Integrated Products

Il numero della parte 48SWTQFN-EP
Spiegazioni elettronici  3.12Gbps GMSL Deserializers for Coax or STP Input and MIPI CSI-2 Output
PDF  103 Pages
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Produttore elettronici  MAXIM [Maxim Integrated Products]
Homepage  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

48SWTQFN-EP Scheda tecnica(HTML) 12 Page - Maxim Integrated Products

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(VAVDD18 = VDVDD18 = 1.7V to 1.9V, VAVDD3 = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω ±1% (differential), EP connected
to PCB ground (GND), TA = -40°C to +105°C, unless otherwise noted. Typical values are at VAVDD18 = VDVDD18 = VIOVDD = 1.8V,
VAVDD3 = 3.3V, TA = +25°C.)
MAX9288/MAX9290
3.12Gbps GMSL Deserializers
for Coax or STP Input and MIPI CSI-2 Output
www.maximintegrated.com
Maxim Integrated │ 12
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I2C/UART PORT TIMING
I2C/UART Bit Rate
9.6
1000
kbps
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD
20
150
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF, 1kΩ
pullup to VIOVDD
20
150
ns
I2C TIMING (Figure 6)
SCL Clock Frequency
fSCL
Low fSCL range:
(I2CMSTBT = 010, I2CSLVSH = 10)
9.6
100
kHz
Mid fSCL range:
(I2CMSTBT 101, I2CSLVSH = 01)
> 100
400
High fSCL range:
(I2CMSTBT = 111, I2CSLVSH = 00)
> 400
1000
START Condition Hold Time
tHD:STA fSCL range
Low
4.0
µs
Mid
0.6
High
0.26
Low Period of SCL Clock
tLOW
fSCL range
Low
4.7
µs
Mid
1.3
High
0.5
High Period of SCL Clock
tHIGH
fSCL range
Low
4.0
µs
Mid
0.6
High
0.26
Repeated START Condition
Setup Time
tSU:STA
fSCL range
Low
4.7
µs
Mid
0.6
High
0.26
Data Hold Time
tHD:DAT fSCL range
Low
0
µs
Mid
0
High
0
Data Setup Time
tSU:DAT
fSCL range
Low
250
ns
Mid
100
High
50
Setup Time for STOP Condition
tSU:STO fSCL range
Low
4.0
µs
Mid
0.6
High
0.26
Bus Free Time
tBUF
fSCL range
Low
4.7
µs
Mid
1.3
High
0.5
Data Valid Time
tVD:DAT
fSCL range
Low
3.45
µs
Mid
0.9
High
0.45
AC Electrical Characteristics



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