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DS1621S/T&R Scheda tecnica(PDF) 16 Page - Maxim Integrated Products |
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DS1621S/T&R Scheda tecnica(HTML) 16 Page - Maxim Integrated Products |
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16 / 16 page ![]() DS1621 NOTES: 1. All voltages are referenced to ground. 2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off. 3. ICC specified with TOUT pin open. 4. ICC specified with VCC at 5.0V and SDA, SCL = 5.0V, 0°C to 70°C. 5. After this period, the first clock pulse is generated. 6. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. 9. CB —total capacitance of one bus line in pF. 10. Writing to the nonvolatile memory should only take place in the 0°C to 70°C temperature range. TIMING DIAGRAM Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ©2015 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. 16 of 16 |
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