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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STM8S103F2 Scheda tecnica(PDF) 82 Page - STMicroelectronics |
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STM8S103F2 Scheda tecnica(HTML) 82 Page - STMicroelectronics |
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82 / 121 page  Electrical characteristics STM8S103F2 STM8S103F3 STM8S103K3 82/121 DocID15441 Rev 14 10.3.10 10-bit ADC characteristics Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit fADC ADC clock frequency VDD= 2.95 to 5.5 V 1 - 4 MHz VDD= 4.5 to 5.5 V 1 - 6 VAIN Conversion voltage range(1) 1. During the sample time, the sampling capacitance, CAIN (3 pF max), can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. - VSS - VDD V CADC Internal sample and hold capacitor -- 3 - pF tS(1) Minimum sampling time fADC = 4 MHz - 0.75 - µs fADC = 6 MHz - 0.5 - tSTAB Wakeup time from standby - - 7.0 - µs tCONV Minimum total conversion time (including sampling time, 10- bit resolution) fADC = 4 MHz 3.5 µs fADC = 6 MHz 2.33 µs -14 1/fADC |
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