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SPC572L64F2 Scheda tecnica(PDF) 73 Page - STMicroelectronics |
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SPC572L64F2 Scheda tecnica(HTML) 73 Page - STMicroelectronics |
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73 / 112 page ![]() DocID027866 Rev 5 73/112 SPC572Lx Electrical characteristics 111 Figure 23. JTAG boundary scan timing 3.17.1.2 Nexus interface timing TCK Output Signals Input Signals Output Signals 11 12 13 14 15 Table 39. Nexus debug port timing(1) # Symbol C Characteristic Value Unit Min Max 7tEVTIPW CC D EVTI pulse width 4 — tCYC(2) 8tEVTOPW CC D EVTO pulse width 40 — ns 9tTCYC CC D TCK cycle time 2(3),(4) —tCYC(2) 9tTCYC CC D Absolute minimum TCK cycle time(5) (TDO/TDOC sampled on posedge of TCK) 40(6) —ns Absolute minimum TCK cycle time(7) (TDO/TDOC sampled on negedge of TCK) 20(6) — 11(8) tNTDIS CC D TDI/TDIC data setup time 5 — ns |
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