STM32WB15CC datasheet(56/127 Pages) STMICROELECTRONICS

Il numero della parte	STM32WB15CC

Spiegazioni elettronici	Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4 with FPU, Bluetooth® 5.2 radio solution

PDF	127 Pages

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Produttore elettronici	STMICROELECTRONICS [STMicroelectronics]

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Memory mapping

STM32WB15CC

56/127

DS13258 Rev 4

Memory mapping

The STM32WB15CC devices feature a single physical address space that can be accessed

by the application processor and by the RF subsystem.

A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,

exclusively accessible by the CPU2, protected against execution, read and write from CPU1

and DMA.

In case of shared resources the SW has to implement arbitration mechanism to avoid

access conflicts. This happens for peripherals Reset and clock controller (RCC), Power

controller (PWC), EXTI and Flash interface, and can be implemented using the built-in

semaphore block (HSEM).

By default the RF subsystem and CPU2 operate in secure mode. This implies that part of

the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by

the CPU2. In this case the Host processor (CPU1) has no access to these resources.

The detailed memory map and the peripheral mapping of the STM32WB15CC devices can

be found in the reference manual RM0473.

STM32WB15CC Scheda tecnica(PDF) 56 Page - STMicroelectronics