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STM32WB50CG Scheda tecnica(PDF) 108 Page - STMicroelectronics |
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STM32WB50CG Scheda tecnica(HTML) 108 Page - STMicroelectronics |
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108 / 119 page ![]() Electrical characteristics STM32WB50CG STM32WB30CE 108/119 DS13047 Rev 5 Figure 24. SPI timing diagram - slave mode and CPHA = 0 Figure 25. SPI timing diagram - slave mode and CPHA = 1 1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD. (SI) MSB IN BIT1 IN LSB IN BIT6 OUT MSB OUT LSB OUT NSS input MOSI INPUT MISO OUTPUT (SI) ai14135b NSS input tSU(NSS) tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) ta(SO) tv(SO) th(SO) tr(SCK) tf(SCK) tdis(SO) MISO OUTPUT MOSI INPUT tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB OUT LSB IN BIT 1 IN |
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