Reading from multiple registers (page reading)

Similarly to multiple (page) writing, reading from subsequent registers relies on auto-increment of the register: the

master can extend data reading to the following registers by generating and ACK pulse at the end of each byte.

Data reading starts immediately and the stream is terminated by a NACK pulse at the end of the last data byte,

followed by a STOP condition (Figure 13).

5.9

Register map

The STWLC68 can be monitored and controlled by accessing the internal registers via I2C interface. The

following registers map reports the accessible addresses. Registers marked with † are read-only and should

not be altered by the user. Addresses not shown in the map and blank bits have to be considered reserved and

not altered as well.

Register

Address

Register name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0000

Chip ID

0x0001

0x0002

Chip Revision

0x0006

ROM ID

0x0007

0x0008

OTP memory configuration ID

0x0009

0x000A

Production trimming version ID

0x000B

0x000C

OTP patch version ID

STWLC68

Register map

DS13131 - Rev 3

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