6

Table 3. Pin Definitions for HDMP-0482.

Pin Name

Pin

Pin Type

Pin Description

TO_NODE[0]+

20

HS_OUT

Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable input.

TO_NODE[0]-

19

TO_NODE[1]+

23

TO_NODE[1]-

22

TO_NODE[2]+

32

TO_NODE[2]-

31

TO_NODE[3]+

35

TO_NODE[3]-

34

TO_NODE[4]+

44

TO_NODE[4]-

43

TO_NODE[5]+

47

TO_NODE[5]-

46

TO_NODE[6]+

57

TO_NODE[6]-

56

TO_NODE[7]+

60

TO_NODE[7]-

59

FM_NODE[0]+

16

HS_IN

Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable output.

FM_NODE[0]-

15

FM_NODE[1]+

26

FM_NODE[1]-

25

FM_NODE[2]+

29

FM_NODE[2]-

28

FM_NODE[3]+

38

FM_NODE[3]-

37

FM_NODE[4]+

41

FM_NODE[4]-

40

FM_NODE[5]+

51

FM_NODE[5]-

50

FM_NODE[6]+

54

FM_NODE[6]-

53

FM_NODE[7]+

63

FM_NODE[7]-

62

BYPASS[0]-

13

I-LVTTL

Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND through a1k

Ω resistor.

BYPASS[1]-

24

For “disk in loop” mode, float HIGH.

BYPASS[2]-

30

BYPASS[3]-

36

BYPASS[4]-

42

BYPASS[5]-

49

BYPASS[6]-

55

BYPASS[7]-

1

REFCLK

2

I-LVTTL

Reference Clock: A user-supplied clock reference used for frequency acquisition in

the Clock and Data Recovery (CDR) circuit.

CPLL1

10

C

Loop Filter Capacitor: A loop filter capacitor for the internal Clock and Data Recovery (CDR) circuit

CPLL0

11

must be connected across the CPLL1 and CPLL0 pins. Recommended value is 0.1

µF.

FM_NODE[7]_AV

14

O-LVTTL

Amplitude Valid: Indicates acceptable signal amplitude on the FM_NODE[7]

± inputs.

If (FM_NODE[7]+ - FM_NODE[7]-) >= 400 mV peak-to-peak, FM_NODE[7]_AV = 1

If 400 mV > (FM_NODE[7]+ - FM_NODE[7]-) > 100 mV, FM_NODE[7]_AV = unpredictable

If 100 mV >= (FM_NODE[7]+ - FM_NODE[7]-),

FM_NODE[7]_AV = 0

FM_NODE[0]_DV

4

O-LVTTL

Data Valid: Indicates valid Fibre Channel Data on the FM_NODE[0]

± inputs when HIGH. Indicates

either run length violation error or no comma detected when LOW.

RFCM

3

I-LVTTL

Reference Clock Mode: To configure a one-twentieth-rate reference clock, connect RFCM to

GND through a 1k

Ω resistor. To configure a one-tenth-rate reference clock, float RFCM HIGH.

MODE_VDD

7

I_LVTTL

Valid Data Detect Mode: To allow data valid detection, float MODE_VDD HIGH. To configure chip for

“CDR anywhere” capability, connect MODE_VDD to GND through a 1k

Ω resistor.

FSEL

12

I_LVTTL

Frame Select: To configure single-frame operation of the data valid and amplitude valid

detection circuits, connect FSEL to GND through a 1k resistor. To configure multi-frame (4-frame)

operation of the data valid and amplitude valid detection circuits, float FSEL HIGH.

Table 3 is continued on next page.