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IC89C54 Scheda tecnica(PDF) 21 Page - Integrated Circuit Solution Inc |
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IC89C54 Scheda tecnica(HTML) 21 Page - Integrated Circuit Solution Inc |
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21 / 24 page ![]() IC89C54/58/64 Integrated Circuit Solution Inc. 21 MC009-0B Figure 16. Programming Timing P3[7:6] P2[7:6] P3.5 VPP tCVPL tBLCX tPLBL tBLBH tSHPL tBHSL tBLAX tCQCV tSLCV tCXQX 0CH/0DH(2) 0EH(1) P3[3:2] P2[5:0] P1[7:0] PROG P0[7-0] P3.4(BUSY) tAVPL tPLTL tBLTH tBLDX tAVQV tAXQX Valid Address(3) Valid Address(3) tBLPH tDVPL Valid Data(4) Valid Data 1. 0EH is for code memory programming. In lock bits programming, 0FH, 03H, 05H, respect to lock bits 1, 2, 3. 2. 0CH is for code memory verification and 0DH is for concurrent memory verification. 09H is for Lock bits verification. 3. Address don’t care while lock bits’ programming or verification. 4. Data don’t care while lock bits’ programming. |
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