AD9956/PCB

Rev. 0 | Page 7 of 12

CLOCK DRIVER CONTROL, PHASE-FREQUENCY

DETECTOR & CHARGE PUMP DIALOG BOX

This dialog box controls the phase detector, charge pump, and

PECL driver components of the device. Use this dialog box to

modify the parameters that control these functions. The dialog

box has two sections: (CML) Clock Driver and Phase-

Frequency Detector/Charge Pump

, shown in Figure 6.

Figure 6. Clock Driver Control, Phase-Frequency Detector &

Charge Pump Dialog Box

(CML) Clock Driver

The on-chip clock driver is current-mode logic (CML) that is

PECL-compliant when properly terminated. The driver can

operate at up to 650 MHz.

To power down the CML driver, select the Clock Driver Power

Down

check box.

Use the Input Select section to specify the signal that is fed to

the input of the CML driver. Select RF Divider Input (REFCLK),

RF Divider Output

(SYSCLK), or the OSC Input.

The full-scale output current for the CML driver is normally

programmed by connecting an external resistor from the DUT

pin, DRV_RSET, to analog ground. However, if you want to use

an internal current programming resistor, select Use Internal

Rset

.

Use the Adding Rise Surge Current and Adding Falling Surge

Current

drop-down menus to change the slew rate of the

output of the PECL driver in response to different capacitive

loads to critically damp the response. See the AD9956 data

sheet for a description of how these values impact the slew rate.

Phase-Frequency Detector/Charge Pump

This section controls the PLL components of the AD9956 and

the CML (PECL-compliant when properly terminated) clock

driver circuits. The first two check boxes allow you to power

down the phase detector and charge pump.

Select Charge Pump Full Powerdown to power down the

entire charge pump. A delay occurs when coming out of this

power-down to reestablish the correct charge pump current.

Select Charge Pump Quick Powerdown to power down the

phase-detector logic while keeping the charge pump current

flowing. No settling time is needed to reestablish the charge

pump current.

Select Enable Crystal Oscillator to turn on an oscillator

function in the phase detector REFERENCE input. When this

function is selected, you can use an external crystal on the

REFERENCE input to stimulate an internal oscillator as the

reference for the PLL.

Move the Charge Pump Current slider to set the multiplier

value for the charge pump reference current. The actual current

from the charge pump, based on the external Rset value, is

shown beneath the slider. The charge pump reference current is

equal to 1.51/CP_Rset, in mA, by the default setting of 3.09 kΩ

on the evaluation board. The base output current of the charge

pump is 500 µA, which can be gained up to 4 mA. The charge

pump polarity changes the loop polarity for a ground-

referenced VCO or a supply-referenced VCO.

The phase detector IF prescalers, Divider N and Divider M, set

the divide-by value on the inputs to the phase detector. The

dividers operate at up to 650 MHz, although the phase detector

inputs themselves operate only up to 200 MHz. You must use

these dividers for any frequencies sent to the phase detector

beyond 200 MHz.

The Pll Lock Detect Ctrl section controls the lock detect

functionality of the AD9956. To enable the lock detect signal,

select the Lock Detect Enable check box. The lock detect signal

can work in two modes. When you select Lock Detect, Logic 1

indicates that the loop has achieved a locked state, and Logic 0

indicates that the loop is unlocked. When you select Phase

Polarity

, Logic 0 indicates that the reference signal leads the

feedback signal, and Logic 1 indicates that the reference signal

lags behind the feedback signal.