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ADM7151ARDZ-02-R7 Scheda tecnica(PDF) 21 Page - Analog Devices

Il numero della parte ADM7151ARDZ-02-R7
Spiegazioni elettronici  800 mA Ultralow Noise, High PSRR, RF Linear Regulator
PDF  24 Pages
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADM7151ARDZ-02-R7 Scheda tecnica(HTML) 21 Page - Analog Devices

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Data Sheet
ADM7151
Rev. B | Page 21 of 24
TOTAL POWER DISSIPATION (W)
2.8
2.6
2.4
3.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
25
155
145
125
102
85
65
45
135
115
95
75
55
35
6400mm2
500mm2
25mm2
TJ MAX
Figure 64. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
TOTAL POWER DISSIPATION (W)
1.8
2.0
2.2
2.4
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
50
60
70
80
90
100
110
120
130
160
150
140
6400mm2
500mm2
25mm2
TJ MAX
Figure 65. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
TOTAL POWER DISSIPATION (W)
2.0
1.6
1.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
65
75
85
95
105
115
125
135
155
145
6400mm2
500mm2
25mm2
TJ MAX
Figure 66. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Thermal Characterization Parameter (ΨJB)
When the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 67 and Figure 68). Maximum
junction temperature (TJ) is calculated from the board
temperature (TB) and power dissipation (PD) using the following
formula:
TJ = TB + (PD × ΨJB)
(5)
The typical value of ΨJB is 15.1°C/W for the 8-lead LFCSP
package and 17.9°C/W for the 8-lead SOIC package.
TOTAL POWER DISSIPATION (W)
9.0
8.5
8.0
7.0
6.0
7.5
6.5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
160
140
120
100
80
60
40
20
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
Figure 67. Junction Temperature vs. Total Power Dissipation for
the 8-Lead LFCSP
TOTAL POWER DISSIPATION (W)
5.5
7.5
7.0
6.5
6.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
160
140
120
100
80
60
40
20
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
Figure 68. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC



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