SP9840 datasheet(9/10 Pages) SIPEX

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The four digital control input pins have been

designed to accept TTL (0.8V to 2.0V minimum)

or full 5V CMOS input levels. The serial data

output can drive either TTL or CMOS inputs.

Timing information is shown in Figure 3. Serial

data is fully clocked into the shift–register after 12

clock rising edges, subject to the described setup

and hold times. After the shift–register data is

valid, the LOADH line can be pulsed high to load

data into the desired DAC data register, which

switches the DAC to the new input code. The serial

clock input should not see a rising edge while the

LOADH pulse is high in order to prevent shift–

The serial clock and data input pins are designed to be

compatibleasslavesunderNationalSemiconductor's

Microwire™ and MicrowirePlus™ protocols and

under Motorola's SPI™ and QSPI™ protocols. In

somemicro–controllers,theinterfaceiscompletedby

programming a bit in a general–purpose I/O port as a

level, used to strobe the LOADH line at the DACs.

This is done in a manner similar to that used for

generating a Chip Select signal, which is necessary

when driving some other Microwire™ peripherals.

Figure 3. Timing

CHARACTERISTICS

(Typical @ 25

°C with V

DD = +5V unless otherwise noted.)

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

Input Clock Pulse Width (t

CH, tCL)50

Data Setup Time (t

DS)30

Data Hold Time (t

DH)20

CLK to SDO Propagation Delay (t

PD)

100

DAC Register Load Pulse Width (t

LD)50

Preset Pulse Width (t

PR)50

Clock Edge to Load Time (t

CKLD)30

Load Edge to Next Clock Edge (tLDCK)

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

SDI

CLOCK

LOAD

OUT

(FFH)

(08H)

SERIAL

DATA IN

SERIAL DATA INPUT TIMING DETAIL (PRESET = Logic "1"; VIN(X) = 1.5V; VREFL = 0V)

SERIAL

DATA OUT

CLOCK

LOAD

VOUT

tDS

tCH

tCL

tLD

tLDCK

±1 LSB

ERROR BAND

tCLKD

tPD

tDH

AX or DX

PRESET

tPR

±1 LSB

ERROR BAND

(FFH)

(08H)

VOUT

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