VSC8540RT datasheet(42/87 Pages) MICROCHIP

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VSC8540RT

DS60001603E-page 42

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6.2.12

BYPASS CONTROL

The bits in this register control aspects of functionality in effect when the device is disabled for the purpose of traffic

bypass. The following table shows the settings available.

6.2.13

ERROR COUNTER 1

The bits in register 19 provide an error counter. The following table shows the settings available.

100BASE-TX receive error

Self-clearing bit.

1: Receive error detected.

100BASE-TX transmit error

Self-clearing bit.

1: Transmit error detected.

100BASE-TX SSD error

Self-clearing bit.

1: Start-of-stream delimiter error detected.

100BASE-TX ESD error

Self-clearing bit.

1: End-of-stream delimiter error detected.

7:0 Reserved

Reserved.

TABLE 6-15:

BYPASS CONTROL, ADDRESS 18 (0X12)

Bit

Name

Access

Description

Default

Transmit disable

R/W

1: PHY transmitter disabled.

4B5B encoder/decoder

R/W

1: Bypass 4B/5B encoder/decoder.

Scrambler

R/W

1: Bypass scrambler.

Descrambler

R/W

1: Bypass descrambler.

PCS receive

R/W

1: Bypass PCS receiver.

PCS transmit

R/W

1: Bypass PCS transmit.

LFI timer

R/W

1: Bypass Link Fail Inhibit (LFI) timer.

Reserved

Reserved.

HP Auto-MDIX at forced 10/

100

R/W

Sticky bit.

1: Disable HP Auto-MDIX at forced 10/100 speeds.

Reserved

R/W

Reserved.

Disable pair swap correction

(HP Auto-MDIX when auto-

negotiation enabled)

R/W

Sticky bit.

1: Disable the automatic pair swap correction.

Disable polarity correction

R/W

Sticky bit.

1: Disable polarity inversion correction on each subchannel.

Parallel detect control

R/W

Sticky bit.

1: Do not ignore advertised ability.

0: Ignore advertised ability.

2:0 Reserved

Reserved.

TABLE 6-16:

EXTENDED CONTROL AND STATUS, ADDRESS 19 (0X13)

Bit

Name

Access

Description

Default

15:8 Reserved

Reserved.

7:0

Receive error counter

8-bit counter that saturates when it reaches 255.

These bits are self-clearing when read.

0x00

TABLE 6-14:

100BASE-TX STATUS EXTENSION, ADDRESS 16 (0X10) (CONTINUED)

Bit

Name

Access

Description

Default

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