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ICS950218 Scheda tecnica(PDF) 13 Page - Integrated Circuit Systems |
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ICS950218 Scheda tecnica(HTML) 13 Page - Integrated Circuit Systems |
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13 / 19 page ![]() 13 Integrated Circuit Systems, Inc. ICS950218 0466B—03/17/04 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Byte 23: Slew Rate Control Register t i Be m a ND W Pn o i t p i r c s e D 7 t i Bd e v r e s e RX d e v r e s e R 6 t i Bd e v r e s e RX 5 t i Bd e v r e s e R1 4 t i Bd e v r e s e R0 3 t i B1 w e l S z H M 8 41 . s t i b l o r t n o c e t a r w e l s k c o l c z H M 8 4 k k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 2 t i B0 w e l S z H M 8 40 1 t i B1 w e l S z H M 8 4 _ 4 21 . s t i b l o r t n o c e t a r w e l s k c o l c z H M 8 4 _ 4 2 k a e w = 0 1 ; l a m r o n = 1 1 : g n o r t s = 1 0 0 t i B0 w e l S z H M 8 4 _ 4 20 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage VIH 2 VDD + 0.3 V Input Low Voltage VIL VSS - 0.3 0.8 V Input High Current IIH VIN = VDD -5 5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 IDD3.3OP1 CL = 0pF; Select @ 66 MHz 90 100 IDD3.3OP2 CL = Full load; Select @ 100 MHz 230 360 IDD3.3OP3 CL =Full load; Select @ 133 MHz 233 360 Powerdown Current IDD3.3PD IREF=5 mA 38.1 45 Input Frequency Fi VDD = 3.3 V 14.32 MHz Pin Inductance Lpin 7nH CIN Logic Inputs 5pF COUT Output pin capacitance 6pF CINX X1 & X2 pins 27 36 45 pF Transition time 1 Ttrans To 1st crossing of target frequency 3ms Settling time 1 Ts From 1st crossing to 1% target frequency 3ms Clk Stabilization 1 TSTAB From VDD = 3.3 V to 1% target frequency 13 ms tPZH,tPZL Output enable delay (all outputs) 110 ns tPHZ,tPLZ Output disable delay (all outputs) 110 ns 1Guaranteed by design, not 100% tested in production. Delay 1 Input Capacitance 1 Input Low Current mA Operating Supply Current µΑ |
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