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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SWCS049F Scheda tecnica(PDF) 35 Page - Texas Instruments |
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SWCS049F Scheda tecnica(HTML) 35 Page - Texas Instruments |
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35 / 144 page  35 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Specifications Copyright © 2010–2018, Texas Instruments Incorporated 5.21 Timing and Switching Characteristics 5.21.1 I 2C Timing and Switching In Table 5-1, SDA is the SDA_SDI or EN2 signal and SCL is the SCL_SCK or EN1 signal. The input timing requirements are given by considering a rising or falling time of 80 ns in high–speed mode (3.4 Mbps), 300 ns in fast–speed mode (400 kbps), 1000 ns in standard mode (100 kbps). Values are over the operating free-air temperature range unless otherwise noted. Table 5-1. Timing Requirements: I2C Interface and Control Signals NO. MIN NOM MAX UNIT INT1 rise and fall times CL = 5 to 35 pF 5 10 ns NRESPWRON rise and fall times CL = 5 to 35 pF 5 10 ns SLAVE HIGH–SPEED MODE SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 100 pF 10 80 ns Data rate 3.4 Mbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 10 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 70 ns I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 160 ns I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 160 ns I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 160 ns SLAVE FAST MODE SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 400 pF 20 + 0.1 × CL 250 ns Data rate 400 Kbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 100 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 0.9 µs I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 0.6 µs I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 0.6 µs I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 0.6 µs SLAVE STANDARD MODE SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 400 pF 250 ns Data rate 100 Kbps I3 tsu(SDA-SCLH) Setup time, SDA valid to SCL high 250 ns I4 th(SCLL-SDA) Hold time, SDA valid from SCL low 0 µs I7 tsu(SCLH-SDAL) Setup time, SCL high to SDA low 4.7 µs I8 th(SDAL-SCLL) Hold time, SCL low from SDA low 4 µs I9 tsu(SDAH-SCLH) Setup time, SDA high to SCL high 4 µs |
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