TUSB2E11 datasheet(49/58 Pages) TI

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12 Power Supply Recommendations

12.1 Power Up Reset

RESETB pin is active low reset pin and can also be used as a power down pin.

TUSB2E11 does not have power supply sequence requirements between VDD3V3 and VDD1V8.

Maximum VDD3V3 and VDD1V8 ramp time to reach minimum supply voltages should be 2 ms.

Digital and analog inputs may be applied when VDD3V3 and VDD1V8 are in unpowered state.

Internal power on reset circuit along with the external RESETB input pin ensures proper initialization when

RESETB is de-asserted high prior to the power rails being valid. If RESETB de-assert high before the power

supplies are stable, internal power on reset circuit will hold off internal reset until the supplies are stable.

I2C/RAP and eUSB2 interfaces will be ready after t_RH_READY upon de-assertion of RESETB or power up.

I2C/RAP and eUSB2 interfaces will be ready after t_RH_READY upon soft reset through the I2C.

Upon de-assertion of RESETB (after t_RH_READY) or software reset (after t_RH_READY), TUSB2E11 will enable and

enter default state and be ready to accept eUSB2 packets, RAP and I2C requests. The repeater will either be in

host repeater mode or device repeater mode depending on the receipt of either host mode enable or peripheral

mode enable.

13 Layout

13.1 Layout Guidelines

1. Place supply bypass capacitors as close to VDD1V8 and VDD3V3 pins as possible and avoid placing the

bypass caps near the eDP/eDN and DP/DN traces.

2. Route the high-speed USB signals using a minimum of vias and corners which reduces signal reflections

and impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the signal’s transmission line and increases the chance of

picking up interference from the other layers of the board. Be careful when designing test points on twisted

pair lines; through-hole pins are not recommended.

3. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

4. Do not route USB traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices or ICs that use or duplicate clock signals.

5. Avoid stubs on the high-speed USB signals due to signal reflections. If a stub is unavoidable, then the stub

must be less than 200 mil.

6. Route all high-speed USB signal traces over continuous GND planes, with no interruptions.

7. Avoid crossing over anti-etch, commonly found with plane splits.

8. Due to high frequencies associated with the USB, a printed circuit board with at least four layers is

recommended; two signal layers separated by a ground and power layer as shown in Figure 13-1.

Signal 1

GND Plane

Power Plane

Signal 2

Figure 13-1. Four-Layer Board Stack-Up

www.ti.com

TUSB2E11

SLLSFI4A – NOVEMBER 2021 – REVISED JUNE 2022

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