HS310x Datasheet

R36DS0011EU0120

Rev.1.2

Aug 10, 2021

Page 11

4.3

The sensor transmission is initiated when the master sends a 0 START bit (S). The transmission is terminated

when the master sends a 1 STOP bit (P). These bits are only transmitted while the SCL line is HIGH (see the

following figure for waveforms).

Once the START condition has been set, the SCL line is toggled at the prescribed data rate, clocking

subsequent data transfers. Data on the SDA line is always sampled on the rising edge of the SCL line and must

remain stable while SCL is HIGH to prevent false START or STOP conditions.

START Condition

STOP Condition

STOP

SDA

SCL

SDA

SCL

START

Figure 14. START and STOP Condition Waveform

After the START bit, the master device sends the 7-bit slave address (see section 4.2) to the HS310x, followed

by the read/write bit, which indicates the transfer direction of any subsequent data. This bit is set to 1 to indicate

a read from slave to master, or set to 0 to indicate a write from master to slave.

All transfers consist of 8 bits and a response bit: 0 for Acknowledge (ACK) or 1 for Not Acknowledge (NACK).

After the ACK is received, another data byte can be transferred or the communication can be stopped with a

STOP bit.

4.4

Measurement Mode

The HS310x is factory-programmed to operate in Sleep Mode. In Sleep Mode, the sensor waits for commands

from the master before taking measurements. The digital core only performs conversions when it receives a

Measurement Request command (MR); otherwise, it is always powered down.

4.5

Measurement Requests (MR)

The MR command is required to wake up the HS310x from its Sleep Mode. Initiate the Measurement Request by

sending the 7-bit slave address followed by an eighth bit = 0 (WRITE).

A measurement cycle consists of a humidity and temperature conversion followed by the digital signal processor

(DSP) correction calculations. At the end of a measurement cycle, the digital output register will be updated

before powering down.

The output is always scaled to 14 bits. The order of the bits is big-endian.

S

Device Slave Address [6:0]

Slave Address Bit

(MSB first)

Start Condition

Stop Condition

Acknowledge (ACK)

Read/Write

(Example: Write = 0)

S

S

W

Wait for

Slave ACK

1

S

0 0

1

0

0

W

(0)

0

A

A

Figure 15. Measurement Request