R5F56609GDFB datasheet(2/123 Pages) RENESAS

2 / 123 page

RX660 Group

1. Overview

R01DS0393EJ0100 Rev.1.00

Page 2 of 123

Mar 18, 2022

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications in outline, and Table 1.2 give a comparison of the functions of products in different

packages.

Table 1.1 is an outline of maximum specifications, and the peripheral modules and the number of channels of the

modules differ depending on the number of pins on the package. For details, see Table 1.2, Comparison of Functions

for Different Packages.

Table 1.1

Outline of Specifications (1/8)

Classification

Module/Function

Description

CPU

 Maximum operating frequency: 120 MHz

 32-bit RX CPU (RXv3)

 Minimum instruction execution time: One instruction per state (cycle of the system

clock)

 Address space: 4-Gbyte linear

 Register set of the CPU

General purpose: Sixteen 32-bit registers

Control: Ten 32-bit registers

Accumulator: Two 72-bit registers

 113 instructions

Instructions installed as standard: 111

Basic instructions: 77

Single-precision floating-point operation instructions: 11

DSP instructions: 23

Instructions for register bank save function: 2

 Addressing modes: 11

 Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

 On-chip 32-bit multiplier: 32 × 32 → 64 bits

 On-chip divider: 32 / 32 → 32 bits

 Barrel shifter: 32 bits

FPU

 Single precision (32-bit) floating point

 Data types and floating-point exceptions in conformance with the IEEE754 standard

function

 Fast collective saving and restoration of the values of CPU registers

 16 save register banks

Memory

Code flash memory

 Capacity: 1 Mbyte/512 Kbytes

 120 MHz, no-wait access

 On-board programming: Four types

 Off-board programming (parallel programmer mode)

 Instructions are executable only for the program stored in the TM target area by using

the Trusted Memory (TM) function and protection against data reading is realized.

Data flash memory

 Capacity: 32 Kbytes

 Programming/erasing: 100,000 times

Unique ID

 12-byte unique ID for the device

RAM

 Capacity: 128 Kbytes

 120 MHz, no-wait access

Operating modes

 Operating modes by the mode-setting pins at the time of release from the reset state

Single-chip mode

Boot mode (for the SCI interface)

Boot mode (for the FINE interface)

User boot mode

 Selection of operating mode by register setting

Single-chip mode

User boot mode

On-chip ROM disabled extended mode

On-chip ROM enabled extended mode

 Endian selectable

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