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• If any of the I/O banks specified for auto-calibration do not have their VDDI/VDDAUX powered on

within the auto-calibration timeout window, then it will be approximately auto-calibrated whenever

VDDI/VDDAUX is subsequently powered on. To obtain an accurate calibration however, on such IO

banks, it is necessary to initiate a re-calibration (using CALIB_START from fabric).

• AVM_ACTIVE only asserts if avionics mode is being used. It is asserted when the later of

DEVICE_INIT_DONE or AUTOCALIB_DONE assert.

6.10.2

Warm Reset Initialization Sequence

The following warm reset timing diagram shows the initialization sequencing of the device when either

DEVRST_N or TAMPER_RESET_DEVICE signals are asserted.

Figure 9 • Warm Reset Timing

6.10.3

Power-On Reset Voltages

The following sections describe the power-on reset voltages.

6.10.3.1

Main Supplies

The start of power-up to functional time (TPUFT) is defined as the point at which the latest of the main

supplies (VDD, VDD18, VDD25) reach the reference voltage levels specified in the following table. This starts

the process of releasing the reset of the device and powering on the FPGA fabric and IOs.

Table 144 • POR Ref Voltages

Note

Power-On Reset Start Point (V)

Supply

Applies to both 1.0 V and 1.05 V opera-

tion.

0.95

VDD

1.71

VDD18

2.25

VDD25

6.10.3.2

I/O-Related Supplies

For the I/Os to become functional (for low speed, sub-400 MHz operation), the (per-bank) I/O supplies

(VDDI, VDDAUX) must reach the trip point voltage levels specified in the following table and the main

supplies above must also be powered on.

111

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AC Switching Characteristics

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