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Agere Systems Inc.

Data Sheet, Rev. 3

May 2004

Two-Cable Transceiver/Arbiter Device

FW802B Low-Power PHY IEEE 1394A-2000

Table of Contents

Contents

Page

Distinguishing Features ...............................................................................................................................................1

Features ......................................................................................................................................................................1

Other Features ............................................................................................................................................................1

Description ..................................................................................................................................................................1

Signal Information .......................................................................................................................................................6

Application Information ..............................................................................................................................................11

Crystal Selection Considerations ..............................................................................................................................12

Load Capacitance .............................................................................................................................................. 13

Adjustment to Crystal Loading ........................................................................................................................... 13

Crystal/Board Layout ..........................................................................................................................................13

1394 Application Support Contact Information ..........................................................................................................13

Absolute Maximum Ratings .......................................................................................................................................14

Electrical Characteristics ...........................................................................................................................................15

Timing Characteristics ...............................................................................................................................................18

Timing Waveforms ....................................................................................................................................................19

Internal Register Configuration ..................................................................................................................................20

Outline Diagrams .......................................................................................................................................................25

64-Pin TQFP ...................................................................................................................................................... 25

Ordering Information .................................................................................................................................................25

List of Figures

Figures

Page

Figure 1. Block Diagram .............................................................................................................................................. 5

Figure 2. Pin Assignments .......................................................................................................................................... 6

Figure 3. Typical External Component Connections ................................................................................................. 11

Figure 4. Typical Port Termination Network .............................................................................................................. 12

Figure 5. Crystal Circuitry ..........................................................................................................................................13

Figure 6. Dn, CTLn, and LREQ Input Setup and Hold Times Waveforms ................................................................ 19

Figure 7. Dn, CTLn Output Delay Relative to SYSCLK Waveforms ......................................................................... 19

List of Tables

Tables

Page

Tables 1. Signal Descriptions ...................................................................................................................................... 7

Tables 2. Absolute Maximum Ratings ....................................................................................................................... 14

Tables 3. Analog Characteristics ............................................................................................................................... 15

Tables 4. Driver Characteristics ................................................................................................................................ 16

Tables 5. Device Characteristics ............................................................................................................................... 17

Tables 6. Switching Characteristics .......................................................................................................................... 18

Tables 7. Clock Characteristics ................................................................................................................................ 18

Tables 8. PHY Register Map for the Cable Environment ......................................................................................... 20

Tables 9. PHY Register Fields for the Cable Environment ....................................................................................... 20

Tables 10. PHY Register Page 0: Port Status Page ................................................................................................22

Tables 11. PHY Register Port Status Page Fields ................................................................................................... 23

Tables 12. PHY Register Page 1: Vendor Identification Page

................................................................................ 24

Tables 13. PHY Register Vendor Identification Page Fields ................................................................................. 24