Tr i p ath Technol ogy, I n c. - Techni cal I n for m ati on

4

TLD4012 – JB/Rev. 2.0a/05.02

ELECTRICAL CHARACTERISTICS

Test/Application Circuits. See functional description for details regarding synthetic output impedance. Minimum and

maximum limits are guaranteed but may not be 100% tested.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Power Consumption

Full-rate, overlapped ADSL signal, line

power = 110 mW (20.4 dBm), with

740

mW

Power Consumption, no signal

LOPWR = Low (see Fig. 1)

250

mW

Power Consumption, no signal, low power

mode

LOPWR = High (see Fig. 1)

130

mW

G.Lite

G.Lite signal, line power = 41.6 mW

(16.2 dBm). See Fig. 1.

390

mW

Disable mode

RESETB = Low

10

mW

Operating Current VDD5

Full-rate, overlapped ADSL signal with

47.0

mA

Operating Current VSS5

Full-rate, overlapped ADSL signal with

49.0

mA

Operating Current VDD15

Full-rate, overlapped ADSL signal with

8.0

mA

Operating Current VSS15

Full-rate, overlapped ADSL signal with

9.5

mA

Quiescent Current (VDD5 and VSS5)

Low

21.7

mA

Quiescent Current (VDD15 and VSS15)

LOPWR = Low

1.1

mA

Quiescent Current (VDD5 and VSS5), low

power mode

LOPWR = High

11.0

mA

Quiescent Current (VDD15 and VSS15),

low power mode

LOPWR = High

0.68

mA

Band-gap Voltage

1.28

V

Differential Output Voltage, peak-to-peak

differential

42

20

V

Differential Output Current

500

mA

Short-circuit Output Current

800

mA

Differential Input Offset Voltage

600

µV

Offset Voltage Drift

30

µV/°C

Differential Output Offset Voltage

Gain = 27.8dB, EN_AC = High, 5k

Ω

across INN and INP

-100

100

mV

Input Bias Current

EN_AC = Low

0.5

µA

Differential Input Bias Current

0.2

µA

Differential Input Resistance

800

k

Ω

Differential Input Capacitance

2

pF

Output Resistance (while in Low-power

mode)

LOPWR = High

0.5

Ω