MX69F1602 datasheet(2/51 Pages) MCNIX

2 / 51 page

P/N:PM0954

MX69F1602/1604C3T/B

REV. 0.5, JUL. 09, 2003

GENERAL DESCRIPTION

The MXIC's mixed multi chip memory combines Flash

and SRAM into a single package. The mixed multi chip

memory operates 2.7 to 3.6V power supply to allow for

simple in-system operation.

The Flash memory of mixed multi chip memory manu-

factured with MXIC's advanced nonvolatile memory tech-

nology, the flash memory of mixed multi chip memory

is designed to be re-programmed and erased in system

or in standard EPROM programmers. The device offers

access times of 70ns/90ns, and 7uA typical standby

current.

Flash memories augment EPROM functionality with in-

circuit electrical erasure and programming and use a

command register to manage this functionality. The com-

mand register allows for 100% TTL level control inputs

and fixed power supply levels during erase and program-

ming, while maintaining maximum EPROM compatibil-

ity.

Flash memory reliably stores memory contents even af-

ter 100,000 erase and program cycles. The cell is de-

signed to optimize the erase and programming mecha-

nisms. In addition, the combination of advanced tunnel

oxide processing and low internal electric fields for erase

and program operations produces reliable cycling.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pin from -1V to VCC + 1V.

The dedicated VPP pin gives complete data protection

when VPP< VPPLK.

The Flash contains both a Command User Interface (CUI)

and a Write State Machine (WSM). A Command User

Interface (CUI) serves as the interface between the sys-

tem processor and internal operation of the device. A

valid command sequence written to the CUI initiates

device automation. An internal Write State Machine

(WSM) automatically executes the algorithms and tim-

ings necessary for erase, word write and sector lock/

unlock configuration operations.

Flash erase automation allows sector erase operation to

be executed using an industry-standard two-write com-

mand sequence to the CUI. A sector erase operation

erases one of the device's 32K-word sectors typically

within 1.0s, 4K-word sectors typically within 0.5s inde-

pendent of other sectors. Each sector can be indepen-

dently erased minimum 100,000 times. Sector erase

suspend mode allows system software to suspend sec-

tor erase to read or write data from any other sector.

Flash program automation allows program operation to

be executed using an industry-standard two-write com-

mand sequence to the CUI. Writing memory data is per-

formed in word increments of the device's 32K-word sec-

tors typically within 0.8s and 4K-word sectors typically

within 0.1s. Word program suspend mode enables the

system to read data or execute code from any other

memory array location.

The Flash features with individual sectors locking by

using a combination of thirty-nine sector lock-bits and

WP, to lock and unlock sectors.

The Flash status register indicates the status of the WSM

when the sector erase, word program or lock configura-

tion operation is done.

The Flash power saving mode feature substantially re-

duces active current when the device is in static mode

(addresses not switching). In this mode, the typical ICCS

current is 7uA (CMOS) at 3.0V VCC. As CEf and R E -

SET are at VCC, ICC CMOS standby mode is enabled.

When RESET is at GND, the reset mode is enabled which

minimize power consumption and provide data write pro-

tection.

The Flash require a reset time (tPHQV) from RESET

switching high until outputs are valid. Similarly, the flash

has a wake time (tPHEL) from RESET-high until writes

to the CUI are recognized. With RESET at GND, the

WSM is reset and the status register is cleared.

The 2M-bit SRAM of MX69F1602C3T/B is organized as

128K-word by 16-bit. The 4M-bit SRAM of

MX69F1604C3T/B is organized 256K-word by 16-bit.The

advanced CMOS technology and circuit techniques pro-

vide both high speed and low power features of with a

typical CMOS standby current of 1uA and maximum

access time of 70ns/85ns in 3V operation.

The mixed multi chip memory is available in 11mm x

8mm FBGA Package to suit a variety of design applica-

tions.

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