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STGAP2D Scheda tecnica(PDF) 10 Page - STMicroelectronics |
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STGAP2D Scheda tecnica(HTML) 10 Page - STMicroelectronics |
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10 / 22 page ![]() Figure 4. Standby state sequences Sequence to enter stand-by mode Sequence to exit stand-by mode t < tSTBY t = tSTBY INA, INB, SD, BRAKE Device status Output ACTIVE STAND-BY SAFE-STATE ACTIVE “stand-by” “stand-by” duration too short t = tSTBY Device status Output ACTIVE STAND-BY SAFE-STATE ACTIVE t > tstbyfilt t < tWUP t > tSTBY tWUP < t < tSTBY t = tawake ACTIVE ACTIVE “stand-by” “stand-by” “stand-by” “stand-by” duration too short duration too long INA = INB = BRAKE = HIGH is any different combination SD = LOW “stand-by”: { INA, INB, SD, BRAKE 5.7 Interlocking function The interlocking function prevents outputs GOUT_A and GOUT_B from being high at the same time, regardless of the status of the input pins INA and INB. In half-bridge topologies this protection avoids shoot-through in case that wrong input signals are generated by the controller device. In case the status of INA and INB is such to require both channels to be ON at the same time, the driver turns both channels off. In some topologies it is required to allow both channels to be ON at the same time: this can be achieved by disabling the interlocking function trough the iLOCK pin. The iLOCK pin shall be either connected to VDD, which enables the interlocking function, or to GND, which disables the interlocking function and allows parallel operation of Channel_A and Channel_B. Refer to Section 5.3 for complete logic inputs truth table. STGAP2D Interlocking function DS12746 - Rev 3 page 10/22 |
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