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LM94021 Scheda tecnica(PDF) 11 Page - National Semiconductor (TI) |
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LM94021 Scheda tecnica(HTML) 11 Page - National Semiconductor (TI) |
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11 / 13 page ![]() 6.0 Selectable Gain for Optimization and In Situ Testing The Gain Select digital inputs can be tied to the rails or can be driven from digital outputs such as microcontroller GPIO pins. In low-supply voltage applications, the ability to reduce the gain to -5.5 mV/˚C allows the LM94021 to operate over the full -50 ˚C to 150 ˚C range. When a larger supply voltage is present, the gain can be increased as high as -13.6 mV/˚C. The larger gain is optimal for reducing the effects of noise (for example, noise coupling on the output line or quantization noise induced by an analog-to-digital converter which may be sampling the LM94021 output). Another application advantage of the digitally selectable gain is the ability to perform dynamic testing of the LM94021 while it is running in a system. By toggling the logic levels of the gain select pins and monitoring the resultant change in the output voltage level, the host system can verify the functionality of the LM94021. www.national.com 11 |
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