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LMK04832PAP/EM Scheda tecnica(PDF) 12 Page - Texas Instruments

Il numero della parte LMK04832PAP/EM
Spiegazioni elettronici  LMK04832-SEP Space Grade Ultra-Low-Noise JESD204B/C Dual-Loop Clock Jitter Cleaner
PDF  103 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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LMK04832PAP/EM Scheda tecnica(HTML) 12 Page - Texas Instruments

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6.7 Timing Diagram
Register programming information on the SDIO pin is clocked into a shift register on each rising edge of the
SCK signal. On the rising edge of the CS* signal, the register is sent from the shift register to the register
addressed. A slew rate of at least 30 V/µs is recommended for these signals. After programming is complete the
CS* signal should be returned to a high state. If the SCK or SDIO lines are toggled while the VCO is in lock, as is
sometimes the case when these lines are shared with other parts, the phase noise may be degraded during this
programming.
4-wire mode read back has same timing as SDIO pin.
R/W bit = 0 is for SPI write. R/W bit = 1 is for SPI read.
SDIO
(WRITE)
SCK
CS*
tc
H
tc
S
td
S
t
SC K
t
H IGH
t
LOW
td
H
SDIO
(Read)
R/W
A14
A13
D1
D0
D1
D0
td
V
A12 to A0,
D7 to D2
D7 to
D2
Figure 6-1. SPI Timing Diagram
LMK04832-SEP
SNAS838 – OCTOBER 2022
www.ti.com
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