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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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STA8090FG Scheda tecnica(PDF) 23 Page - STMicroelectronics |
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STA8090FG Scheda tecnica(HTML) 23 Page - STMicroelectronics |
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23 / 41 page  DS10719 Rev 6 23/41 STA8090FG General description 40 alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update. RTC features 47-bit counter clocked by 32.768 kHz clock 32-bit for the integer part (seconds) and 15-bit for the fractional part The integer part and the fractional part are readable independently The counter, once enabled, can be stopped Integer part load register (32-bit) Fractional part load register (15-bit) Load bit to transfer the content of the entire load register (integer+fractional part) to the 47-bit counter. Once set by the MCU this bits is cleared by the hardware to signal to the MCU that the RTC has been updated. 3.4.11 MSP The STA8090FG provides one MSP transmitter block. Element (data) size from 8 to 32 bits, LSB or MSB first Programmable frequency shift clock for data transfer Direct interface to: – Industry-standard codecs and serially connected A/D and D/A devices – IIS compliant devices – SPI compliant devices Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep |
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