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L99MOD53XP Scheda tecnica(PDF) 15 Page - STMicroelectronics |
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L99MOD53XP Scheda tecnica(HTML) 15 Page - STMicroelectronics |
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15 / 35 page ![]() DS12617 Rev 5 15/35 L99MOD53XP Electrical specifications 34 tCLKL Clock low time VCC = 5 V 400 ns tset CSN CSN setup time, CSN low before rising edge of CLK VCC = 5 V 400 ns tset CLK CLK setup time, CLK high before rising edge of CSN VCC = 5 V 400 ns tset DI DI setup time VCC = 5 V 200 ns thold time DI hold time VCC = 5 V 200 ns tr in Rise time of input signal DI, CLK, CSN VCC = 5 V 100 ns tf in Fall time of input signal DI, CLK, CSN VCC = 5 V 100 ns 1. DI timing parameters tested in production by a passed / failed test: Tj= -40°C / +25°C: SPI communication @ 2 MHz. Tj= +125°C SPI communication @ 1.25 MHz. Table 14. DI timing (continued) Symbol Parameter(1) Test condition Min. Typ. Max. Unit Table 15. DO Symbol Parameter Test condition Min. Typ. Max. Unit VDOL Output low level VCC = 5 V, ID = -2 mA 0.2 0.4 V VDOH Output high level VCC = 5 V, ID = 2 mA VCC -0.4 VCC-0.2 V IDOLK 3-state leakage current VCSN = VCC, 0 V < VDO < VCC -10 10 µA CDO (1) 3-state input capacitance VCSN = VCC, 0 V < VCC < 5.3 V 10 15 pF 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 16. DO timing Symbol Parameter Test condition Min. Typ. Max. Unit tr DO DO rise time CL = 100 pF, Iload = -1 mA 80 140 ns tf DO DO fall time CL = 100 pF, Iload = 1 mA 50 100 ns ten DO tri L DO enable time from 3-state to low level CL = 100 pF, Iload = 1 mA pull-up load to VCC 100 250 ns tdis DO L tri DO disable time from low level to 3-state CL = 100 pF, Iload = 4 mA pull-up load to VCC 380 450 ns ten DO tri H DO enable time from 3-state to high level CL =100 pF, Iload = -1 mA pull-down load to GND 100 250 ns tdis DO H tri DO disable time from high level to 3-state CL = 100 pF, Iload = -4 mA pull-down load to GND 380 450 ns td DO DO delay time VDO < 0.3 VCC, VDO > 0.7 VCC, CL = 100 pF 50 250 ns |
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