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CS47L85 Scheda tecnica(PDF) 30 Page - Cirrus Logic

Il numero della parte CS47L85
Spiegazioni elettronici  Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
PDF  370 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS47L85 Scheda tecnica(HTML) 30 Page - Cirrus Logic

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CS47L85
30
Rev 4.3
TYPICAL PERFORMANCE
TYPICAL POWER CONSUMPTION
Typical power consumption data is provided below for a number of different operating conditions.
Test Conditions:
DBVDD1 = DBVDD2 = DBVDD3 = DBVDD4 = CPVDD1 = AVDD = LDOVDD = 1.8V,
CPVDD2 = DCVDD = FLLVDD = 1.2V, SPKVDDL = SPKVDDR = 4.2V, MICVDD = 2.5V (powered from LDO2),
TA = +25ºC, PGA gain = 0dB, fs = 48kHz, 24-bit audio data, I
2S Slave Mode,
SYSCLK = 24.576 MHz (direct MCLK1) unless otherwise
OPERATING MODE
TEST CONDITIONS
SUPPLY
CURRENT
(1.2V)
SUPPLY
CURRENT
(1.8V)
SUPPLY
CURRENT
(4.2V)
TOTAL
POWER
Music Playback to Headphone
AIF1 to DAC to HPOUT (stereo)
Load = 32
Quiescent
2.2mA
0.7mA
0.0mA
3.9mW
1kHz sine wave, PO=10mW
37.7mA
1.9mA
0.0mA
48.66mW
Music Playback to Earpiece
AIF1 to DAC to HPOUT (mono)
Load = 32
, BTL
Quiescent
1.5mA
0.8mA
0.0mA
3.24mW
1kHz sine wave, PO=30mW
61.8mA
1.8mA
0.0mA
77.4mW
Music Playback to Speaker
AIF1 to DAC to SPKOUT (stereo)
Load = 8
, 22µH, BTL
Quiescent
2.0mA
2.1mA
0.0mA
6.18mW
1kHz sine wave, PO=700mW
2.0mA
2.1mA
382mA
1610mW
Stereo Line Record
Analogue Line to ADC to AIF1
MICVDD=1.8V (CP2/LDO2 bypass)
1kHz sine wave, -1dBFS out
2.1mA
2.4mA
0.0mA
6.84mW
Sleep Mode
Accessory detect enabled
(JD1_ENA=1)
0.00mA
0.01mA
0.000mA
0.018mW



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