V40006901 datasheet(6/63 Pages) TOSHIBA

6 / 63 page

Pinning:

1. Gain control voltage (AGC) : 4.0V, Max:4.5V

2. Tuning voltage

3. I²C-bus address select

: Max:5.5V

4. I²C-bus serial clock

: Min:-0.3V, Max:5.5V

5. I²C-bus serial data

: Min:-0.3V, Max:5.5V

6. Not connected

7. PLL supply voltage

: 5.0V, Min:4.75V, Max:5.5V

8. ADC input

9. Tuner supply voltage

: 33V, Min:30V, Max:35V

10. Symmetrical IF output 1

11. Symmetrical IF output 2

SAW FILTERS

K9453: Two channels switchable sound IF saw filter of BG, DK, I, L systems for input channel 2 and of L´

system for input channel 1.

K3953: Two channel switchable video IF saw filter of BG, DK, I, L systems for input channel 2 and of L´

system for input channel 1.

J3950: Video IF saw filter for I system

DIGITAL TV SOUND PROCESSING

MSP3410D

The MSP3410D is an I2C controlled single-chip multistandard sound processor for applications in analog and digital TV

sets. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out is

performed in a single-chip covering all European TV-standards. It is designed to simultaneously perform digital

demodulation and decoding of NICAM-coded TV stereo sound, as well as demodulation of FM-mono TV sound and two

FM systems according to the German or Korean terrestrial specs. It is also possible to do AM-demodulation according to

the SECAM system. There is AGC for analog inputs: 0.14 - 3Vpp. All demodulation and filtering is performed on chip and

is individually programmable. All digital NICAM standards (B/G, L, and I) are realised. Only one crystal clock (18.432Mhz)

is necessary. External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop

frequency of the internal PLL and for stabilising the frequency in closed-loop operation. The higher the capacitors, the

lower the clock frequency result. The nominal free running frequency should match the centre of the tolerance range

between 18.433 and 18.431Mhz as closely as possible. By means of standardised I2S interface, additional feature

processors (DPL35xx, Dolby Prologic processor for this chassis) can be connected to the IC.

I2S bus interface consists of five pins:

I2S_DA_IN12

for input four channels (two channels per line) per sampling cycle (32Khz).

I2DA_OUT,

for output, two channels per sampling cycle (32KHz).

I2S_CL,

for timing of the transmission of I2S serial data, 1.024Mhz.

I2S_WS,

for the word strobe line defining the left and right sample.

Features:

5-band graphic equalizer (as in MSP3400C)

Enhanced spatial affect (pseudo stereo / base-width enlargement as in MSP3400C)

Headphone channel with balance, bass treble, loudness

Balance for loudspeaker and headphone channels in dB units (optional)

Additional pair of D/A converters for SCART2 out

Improved over-sampling filters (as in MSP 3400C)

Additional SCART input

Full SCART in/out matrix without restrictions

SCART volume in dB units (optional)

Additional I²S input (as in MSP 3400C)

New FM-identification (as in MSP 3400C)

Demodulator short programming

Auto-detection for terrestrial TV-sound standards

Precise bit-error rate indication

Automatic switch from NICAM to FM/AM or vice versa

Improved NICAM synchronisation algorithm

Improved carrier mute algorithm

ImprovedAM-demodulation

ADR together with DRP 3510A

Dolby Pro Logic together with DPL 35xx A

Reduction of necessary controlling

Less external components

Significant reduction of radiation

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