ADF4377 datasheet(34/79 Pages) AD

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Data Sheet

ADF4377

APPLICATIONS INFORMATION

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Rev. 0 | 34 of 79

Figure 87. Theoretical In-Band Phase Noise, fOUT = 10 GHz

POWER-UP AND INITIALIZATION SEQUENCE

Figure 88. Power-Up and Initialization Sequence

The following steps describe the recommended power-up and initi-

alization sequence of the ADF4377:

1. Apply specified voltages to the V5V, V3.3V_1, and V3.3V_2 power

supply groups. The ADF4377 is in full power-down mode at this

point and SPI programming is not possible.

2. Set the CE pin to a logic high. It is acceptable to connect

the CE pin to the V3_LDO pin via a pull-up resistor, therefore

performing Step 1 and Step 2 coincidentally.

3. After waiting ≥200 μs for all SPI register bits to settle to their

power-on reset state (POR), begin programming the SPI to

configure the ADF4377 to a desired state. The following is the

recommended SPI programming:

a. Set the SDO_ACTIVE and CMOS_OV bits to a desired

state for future readback operations.

b. Program all register addresses in descending order,

REG0045 to REG0010. There are several required re-

served register field settings provided in Table 42 that are

required for proper device operation.

4. The ADF4377 remains in power-down mode until the PD_ALL

bit is programmed to 0. After PD_ALL is disabled, wait at least

10 μs for the VCO calibration circuitry and other circuit blocks to

settle before starting a VCO calibration.

5. A write to REG0010 starts a VCO autocalibration. At this point,

the device is fully operational and new frequencies can be

programmed as often as desired.

6. Setting PD_ALL to 1 powers down the ADF4377, retaining

the latest programmed SPI settings and full SPI programming

capability.

7. If only the state of PD_ALL was modified in Step 6, setting

PD_ALL to 0 returns the ADF4377 to the frequency program-

med in Step 5. After a 10 μs wait, all circuit blocks are

completely powered up internally. This 10 μs wait does not

include the frequency settling time associated with the loop filter

bandwidth.

8. Toggling the CE pin level causes the ADF4377 to return to

full power-down mode and return the SPI registers to the POR

state (see Step 2 and Step 3).

POWER SUPPLY AND BYPASSING

The ADF4377 is a high performance, low noise device. Phase

noise and spurious performance may be degraded by noisy power

supplies. To achieve maximum performance and ensure that power

supply noise does not degrade the performance of the ADF4377,

it is recommended to use the Analog Devices low noise, high pow-

er supply rejection ratio (PSRR) regulators. Preferred regulators

include the LT3045, ADM7150, and the ADM7151.

The ADF4377 eliminates the need for on-board supply bypass

capacitors, by integrating all necessary local power supply bypass

capacitors on the ADF4377 package laminate. As shown in Figure

89, by removing the requirement for local power supply bypass

capacitors, the ADF4377 consumes 40% less effective PCB area

and reduces the number of board layout design challenges.

Figure 89. Layout Advantages with Integrated Power Supply Decoupling

Capacitors

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