SY87702L datasheet(6/14 Pages) MICREL

6 / 14 page

SY87702L

Micrel, Inc.

M9999-102405

hbwhelp@micrel.com or (408) 955-1690

FREQSEL1, ..., FREQSEL3 [Frequency Select] – TTL

Inputs

These inputs select the output clock frequency range, as

shown in Table 2.

VCOCLK

FREQSEL1

FREQSEL2

FREQSEL3

Divider

Table 2.

DIVSEL1, ..., DIVSEL3 [Divider Select] – TTL Inputs

These inputs select the ratio between the output clock

frequency (RCLK/TCLK) and the REFCLK input frequency

as shown in Table 3. Please note that the divide by 32

selection, “011”, is only available for use when FREQSEL

are set to “000.”

REFCLK

DIVSEL1

DIVSEL2

DIVSEL3

Multiplier

Table 3.

CLKSEL [Clock Select] – TTL Input

This input is used to select either the recovered clock of

the receiver PLL (CLKSEL = HIGH) or the clock of the

frequency synthesizer (CLKSEL = LOW) to the TCLK

outputs.

ENPECL [Enable PECL] – TTL Input

This input, when HIGH (ENPECL = 1), enables the

differential PECL outputs TCLKE

± RDOUTE±, and RCLKE±.

It also disables the CML outputs, by setting TCLKC+,

RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC–,

RDOUTC–, and RCLKC– logic LOW.

When set LOW (ENPECL = 0), this signal enables the

differential CML outputs TCLKC

±, RDOUTC±, and RCLKC±.

It also disables the PECL outputs by setting TCLKE+,

RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE–,

RDOUTE–, and RCLKE– logic LOW.

OUTPUTS

LFIN [Link Fault Indicate] – O.C. TTL Output

This output indicates the status of the input data stream

RDIN. LFIN will go HIGH if CD is HIGH and RDIN is within

the frequency range of the Receive PLL (as per ALRSEL).

LFIN is an asynchronous output.

RDOUTE

± [Receive Data Out] – Differential PECL

These ECL 100K outputs represent the recovered data

from the input data stream (RDIN). This recovered data is

sampled on the falling edge of RCLK.

RDOUTC

± [Receive Data Out] – Differential CML

This is the CML version of RDOUTE

±.

RCLKE

± [Receive Clock Out] – Differential PECL

These ECL 100K outputs represent the recovered clock

used to sample the recovered data (RDOUT).

RCLKC

± [Receive Clock Out] – Differential CML

This is the CML version of RCLKE

±.

TCLKE

± [Transmit Clock Out] – Differential PECL

These ECL 100K outputs represent either the recovered

clock (CLKSEL = HIGH) used to sample the recovered data

(RDOUT) or the transmit clock of the frequency synthesizer

(CLKSEL = LOW).

TCLKC

± [Transmit Clock Out] – Differential CML

This is the CML version of TCLKE

±.

INPUTS/OUTPUTS

PLLSN+, PLLSN– [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis narrow-

band PLL.

PLLSW+, PLLSW– [Clock Synthesis Loop Filter]

External loop filter pins for the clock synthesis wide-band

PLLs.

PLLRN+, PLLRN– [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery narrow-

band PLL.

PLLRW+, PLLRW– [Clock Recovery Loop Filter]

External loop filter pins for the clock recovery wide-band

PLLs.

OTHERS

VCC

Supply Voltage

VCCO

Output Supply Voltage

VCCA

Analog Supply Voltage

GND

Ground

GNDA

Analog Ground

These pins are for factory test, and are to be

left unconnected during normal use.

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